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| UvA | Fac. Science | CSA | Thomas A.M. Bernard's Homepage | ||
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The MicroGrids project belongs to the GLANCE programme funded by NWO, GLANCE (english). The objective of GLANCE is to stimulate fundamental research in large scale and distributed systems. The goal of the MicroGrids project is to design a chip-multiprocessor with its tools suite which comprises a chip simulator and compilation tools based on the microthreaded model of concurrency. The Computer Systems Architecture research group is tackling significant problems spanning compilers, computer architecture and implementations as systems on a chip. The scope includes embedded systems, where we are involved in early design space exploration, as well as general purpose computing platforms that we call Microgrids. The factors linking these are the concurrency and various levels of simulation, which we use to evaluate performance as well as power and implementation efficiency. Moore’s law has over the last five decades provided exponential growth in chip densities at an unprecented doubling every 18-24 months. Over the last two decades this wealth of gates has been largely squandered by the industries reluctance to embrace explicit concurrency in microprocessor design to improve performance, relying instead on clock speed, which has resulted in excessive power dissipation and the so called memory wall. There are sound reasons for this direction, as concurrency is intrinsically difficult. The alternative of using hardware to extract and manage concurrency from a sequential instruction stream allows legacy code to drive each new generation of processor. The down side are control and storage structures that scale very badly and this scaling has eventually tolled the death knoll for this approach. In CSA we are developing new microprocessor architectures that are completely scalable in area, performance and power. These are based on a process of code fragmentation, we call microthreads. Each code fragment is managed in the hardware with minimal and above all scalable structures. Along with the concept of Microthreading we are exploring microcontexts and microgrids in order to provide complete solutions to the problems of the highly concurrent microprocessors we expect to see in the near future, i.e. 100s of processors in the next generation and perhaps 100,000 by 2020, by which time CMOS will be at its limit of scaling. Please check back here regularly for a progress update of the project. | 
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European citizens are now living in a world of "pervasive computing", where virtually every object has a processing power. Undoubtedly, computing devices are more ubiquitous and interconnected than ever, fulfilling the most varied tasks with little human intervention. The size of these "pervasive computing" networks is significantly increasing, as well as the variety of the computing devices, both at chip (multicore and reconfigurable architectures) and system level (distributed processing). As their scope of application broadens, processing resources require greater flexibility and scalability to meet the various needs of users. By the year 2020, embedded computing architectures will be far more complex, due mainly to the convergence of High Performance Computing and Embedded Computing technologies, the emergence of new hardware technologies and finally, the multiplication of heterogeneous computing devices. The purpose of the ÆTHER project is to show that self-adaptive computing architectures can be a powerful approach to simultaneously addressing the major problems raised by pervasive computing. ÆTHER's main objectives are to study, evaluate and propose novel computing architectures responding to the most demanding embedded applications in the next 10+ years. In particular, the ÆTHER project aims to tackle the issues related to the performance and technological scalability, increased complexity and programmability of future embedded computing architectures by introducing self-adaptive technologies in computing resources. The ÆTHER consortium will study and propose self-adaptive networked entities (SANE) based on reconfigurable computing architectures, and study their impact at various levels of the computing chain such as operating environments, programming methods and tools and application design. The potential benefits of the proposed approach will be assessed and validated with industrial partners on realistic application scenarios.
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The Apple-CORE Project develops compilers, operating systems and execution platforms to support and evaluate a novel architecture paradigm that can exploit many-core computer systems to the end of silicon. It differs from current approaches by adopting a systematic model of concurrency implemented as instructions in the processors' ISA (developed in the EU FP6 ÆTHER project). This approach has enormous potential but is disruptive. The paradigm shift effectively requires a new infrastructure of tools as the model executes OS kernel functionality as processor instructions. The benefits are large, however, as compilers need only capture concurrency in a virtual way rather than capturing, mapping and scheduling it. This separates the concerns of programming and concurrency engineering and opens the door for successful parallelising compilers. Mapping and scheduling is performed dynamically by implementations of the concurrency control instructions. Particular benefits can be expected for data-parallel and functional programming languages as they expose their concurrency in a way that can be easily captured by a compiler. Another advantage of this approach is the binary compatibility the new processor has with the modified ISA. Moreover, once code is compiled with the new tools, binarycode is executable on an arbitrary numbers of processors and hence provides future binary-code compatibility as well as enabling dynamic resource mapping to binary programs from a pool of processors. The concurrency controls also allow for management of partial failure, which together with the binary-code compatibility provide the necessary support for reliable systems. Finally, this approach exposes information about the work to be executed on each processor and how much can be executed at any given time. This information can provide powerful mechanisms for the management of power by load balancing processors based on clock/frequency scaling. The objective of developing this infrastructure is to evaluate the model and provide opportunities to exploit the results of this research in a variety of markets, including embedded and commodity processors, and also high-performance applications. In particular, the binary compatibility provides a unique opportunity to make an impact on commodity processors in Europe. |
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