PDF file downloads of recent research papers

Computer architecture - microgrids, microthreaded processors and networks

T.A.M. Bernard, C. Grelck, M. Hicks, C.R. Jesshope, and R. Poss (2009) Resource-Agnostic Many-core Programming through Hardware/Software Co-Design, submitted to Computing Frontiers 2010.

M. Lankamp, T.A.M. Bernard, M. Hicks, C. Jesshope and L. Zhang (2009) Evaluation of a hardware implementation of the SVP concurrency model, submitted to ISCA 2010.

Chris JESSHOPE, Michael HICKS, Mike LANKAMP, Raphael POSS and Li ZHANG (2009) Making multi-cores mainstream – from security to scalability, to be published Proc Parco 2009

C. Jesshope, M. Lankamp and L Zhang (2009) Evaluating CMPs and their memory architecture, Proc. Architecture of Computing Systems, ARCS 2009, LNCS 5455, (Eds. M Berekovic, C. Muller-Schoer, C. Hochberger and S. Wong), pp246-257.

C. R. Jesshope and A. Shafarenko (2008) Concurrency engineering, Proc. 13th IEEE Asia-Pacific Computer Systems Architecture Conference (ACSAC 2008), ISBN: 978-1-4244-2683-6.

fication of the on-chip COMA cache coherence protocol, Proc. AMAST 2008 - Algebraic Methodology and Software Technology, ISBN 978-3-540-79979-5, pp413-429.

T. Bernard, K. Bousias, L. Guang, C. R. Jesshope, M. Lankamp, M. W. van Tol and L. Zhang (2008) A general model of concurrency and its implementation as many-core dynamic RISC processors, Proc. Intl.Conf. on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008 (Eds. W. Najjar and H. Blume), ISBN: 978-1-4244-1985-2, pp1-9.

C. R. Jesshope, J-M Philippe and M. van Tol (2008) An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency, Proc. Intl. Workshops on Embedded Computer Systems: Architecture, Modeling and Simulation, SAMOS-2008 (Eds. M. Berekovic, N. Dimopoulos and S. Wong), LNCS 5114, pp218-228.

C. Jesshope (2008) Operating systems in silicon and the dynamic management of resources in many-core chips, Parallel Processing Letters (PPL), 18, (2), pp257 - 274.

M. W. van Tol, C. R. Jesshope, M. Lankamp and S. Polstra (2008) An implementation of the SANE Virtual Processor using POSIX threads, Journal of Systems Architecture, Volume 55, Issue 3, March 2009, pp 162-169.

K. Bousias, L. Guang, C.R. Jesshope, M. Lankamp (2008) Implementation and Evaluation of a Microthread Architecture, Journal of Systems Architecture, Volume 55, Issue 3, March 2009, pp 149-161

C R Jesshope (2008) A model for the design and programming of multi-cores, In Advances in Parallel Computing, 16, High performance Computing and Grids in Action (Ed. L. Grandinetti), IOS Press, ISBN 978-1-58603-839-7, pp37-55.

L. Zhang and C. Jesshope (2007) On-Chip COMA Cache-coherence Protocol for Microgrids of Microthreaded Cores, Eds. Bouge et. al., Proc EuroPar 2007 Workshops, LNCS Volume 4854, Springer, pp 38-48

T.D Vu and C. R. Jesshope (2007) Formalizing SANE virtual processor in thread algebra, in M. Butler, M. G. Hinchley and M. M. Larrondo-Petrie, eds. ICFEM 2007, pp 345-365.

Thuy Duong Vu1 and C R Jesshope2 (2007) Thread algebra for SANE Virtual Processors, to be published

C R Jesshope (2007) SVP and µTC - A dynamic model of concurrency and its implementation as a compiler target, draft report (unpublished)

Bell I., Hasasneh N. M. and Jesshope C. R. (2006) Asynchronous arbiter for micro-threaded Chip multiprocessors, to be published, Journal of Systems Architecture.

C R Jesshope (2006) µTC – an intermediate language for programming chip multiprocessors, Proc. Pacific Computer Systems Architecture Conference 2006 - ACSAC06, ISBN 3-540-4005, LNCS 4186, pp147-160..

Bell, I, Hasaasneh, N and Jesshope C R (2006) Supporting Microthread Scheduling and Synchronisation in CMPs. Intl. J Parallel Processing, Jan 2006, pp1-9, DOI 10.1007/s10766-006-0017-y, URL: http://dx.doi.org/10.1007/s10766-006-0017-y

Jesshope C. R. (2006) Microthreading a model for distributed instruction-level concurrency, Parallel processing Letters, 16(2), pp209-228.

Hasasneh N M, Bell, I and Jesshope C R (2006) Scalable and Partitionable Asynchronous Arbiter for Micro-threaded Chip Multiprocessors, Proc. Architecture of Computing Systems - ARCS 2006, ISBN: 3-540-32765-7, pp. 252 - 267 (Frankfurt/Main, Germany, March 13-16).

T. Bernard, K. Bousias, B. de Geus, M. Lankamp, L. Zhang, A. Pimentel, P.M.W. Knijnenburg, and C.R. Jesshope (2006) A Microthreaded Architecture and its Compiler, Proc. 12th International Workshop on Compilers for Parallel Computers (CPC), M. Arenez, R. Doallo, B.B. Fraguela, and J. Tourino (eds.), pp 326-340.

Kostas Bousias and Chris Jesshope(2005) The Challenges of Massive On-Chip Concurrency, Lecture Notes in Computer Science, Volume 3740, pp157 - 170 (see also)

Bousias, K, Hasasneh N M and Jesshope C R (2005) Instruction-level parallelism through Microthreading - a scalable Approach to chip multiprocessors, This is an electronic version of an article to be published in the BCS Computer Journal.
Online access to the Computer Journal abstract and definitive pdf file

Jesshope C. R. (2005) Micro-grids - the exploitation of massive on-chip concurrency, pp 203-223 (Invited paper, HPC 2004Cetraro, June 2004), In Grid Computing: A New Frontier of High Performance Computing, 14, pp203-223, (ed. L. Grandinetti, Elsevier, Amsterdam, 2005).

Jesshope C. R. (2004) Scalable Instruction-level Parallelism, In Computer Systems: Architectures, Modelling and Simulation, Proc 3rd and 4th Int;l. Workshhops, SAMOS 2003, SAMOS 2004, (LNCS 3133, Springer), ISBN 3-540-22377-0, pp383-392, presented Samos, Greece, July 2004.

Jesshope C. R.(2004) A Concurrency Model for Instruction-level Distributed Computing, unpublished.

Jesshope C. R. (2003) Multithreaded microprocessor s – evolution or revolution (Keynote presentation), Proc. ACSAC 2003: Advances in Computer Systems Architecture, Omondo and Sedukhin (Eds.), pp 21-45, Springer, LNCS 2823 (Berlin, Germany), ISSN0302-9743, Aizu, Japan, 22-26 Sept 2003.

Jesshope, C. R. and Luo B. (unpublished 2002) A Microthreaded Chip Multiprocessor with a Vector instruction Set

Luo B and Jesshope. C (2002) Performance of a Micro-threaded Pipeline, Proc. ACSAC 2002 Australia Computer Science Communications, Vol 24,

Jesshope, C. R. (2001) Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines, Proc. ACSAC 2001, Australia Computer Science Communications, Vol 23, No 4., pp80-88, IEEE Computer Society (Los Alimitos, CA, USA), ISBN 0-7695-0954-1

C. R. Jesshope and B. Luo (2000) Micro-threading: A New Approach to Future RISC, Proc ACAC 2000, pp34-41, ISBN 0-7695-0512-0 (IEEE Computer Society press), Canberra Jan 2000

Jesshope C. R. and Shafarenko, A. V. (1998)_Asynchrony in Parallel Computing – A Question of Scale, Proc MPCS '98, Third International Conference on Massively Parallel Computing Systems, Colorado Springs, Colorado USA April 6 - 9, 1998.

A Bolychevsky, C R Jesshope and V B Muchnick, (1996) Dynamic scheduling in RISC architectures, IEE Trans. E, Computers and Digital Techniques ,143, pp309-317.

C R Jesshope, D Barsky, A Bolychevsky and A V Shafarenko (1995) Asynchronous in parallel distributed computing, (Invited paper) Parallel Algorithms/Architecture Synthesis, ISBN 0-8186-7870-4 pp-insert (IEEE Computer Society Press).

C R Jesshope and C Izu (1993) The MP1 network chip and its application to parallel computers, The Computer Journal, 36, pp763-777.

Managed learning environments
Wen, L. and Jesshope, C. R. Web-services technology and learning technology - a web-services model for constructing virtual learning environments, to be published to IWCS 2003.

Jesshope C. R. and Zhang, Z. (2002) A content management system for the TILE managed learning environment, Proc Third International Conf. On Networked Learning, (Eds. Banks, Goodyear, Hodgson and MCConnell), Sheffield University, March 2002, ISBN: 0902831 410, pp136-143.

Jesshope, C. R. (2001) Easy-to-use multimedia tools and scalable distributed architectures for web-based teaching and learning, (keynote presentation) Proc DCABES 2001, Hubei Sci. and Tech. Press, Wuhan, China, ISBN 7-5352-2722-8, pp 52-60. (Keynote paper)

Gehne, R., Jesshope, C. and Zhang, J. (2001) Technology Integrated Learning Environment—A Web-based Distance Learning System, Proc. IASTED Intl Conf on Internet and Multimedia Systems and Applications IMSA-2001, Honolulu, Hawaii, August 13-16, 2001.

C. R. Jesshope (2000) Integrated tools for on-line education, Proc IWALT 2000, ISBN 0-7695-0653-4, IEEE Computer Society( Los Alamitos CA, USA), pp205-8.

Multimedia authoring
Jesshope, C. R. Towards the dynamic publication of multimedia presentations - a strategy for development, to be published in the Proceedings of ALT-C 2003.

Gehne, R and Jesshope, C. R. (2002) Interactive multimedia for dummies, Proc Third International Conf. On Networked Learning, (Banks, Goodyear, Hodgson and MCConnell Eds.), Sheffield University, March 2002, ISBN: 0902831 410, pp144-152.

Jesshope C. R. (2001) Cost-Effective Multimedia in On-line Teaching , in Educational Technology & Society 4 (3) 2001ISSN 1436-4522 also available at: (http://ifets.ieee.org/periodical/vol_3_2001/jesshope.html)

C. R. Jesshope (2000) The use of streaming multi-media in microelectronic education, Microelectronics Education, Kluwer Academic (London), ISBN 0 7923 6456 2, pp45-48

C. R. Jesshope (2000) The use of multi-media in internal and extramural teaching, Proc Lifelong Learning Conference, Central University of Queensland (Brisbane, Australia), ISBN 187 6674 06 7, pp257-262.

R. Gehne and C. R. Jesshope (2000) Tools for the production of small-footprint, low-bandwidth, streaming multi-media for distance education, Proc Lifelong Learning Conference, Central University of Queensland (Brisbane, Australia), ISBN 187 6674 06 7, pp240-244.

C. R. Jesshope, A. Shafarenko and H. Slusanschi (1998) Low-bandwidth multimedia tools for web-based lecture publishing, IEE Engineering Science and Educational Journal, 7 (4), pp148-154

Video conferencing
C. R. Jesshope and Y. Q. Liu (2001) High Quality Video Delivery over Local Area Networks With Application to Teaching at a Distance, Intl J. of Electrical Engineering Education (IJEEE), Vol 38(1), ISSN 0020-7209, pp11-25, Manchester University Press.